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參數(shù)資料
| 型號(hào)： | CY7C1484V25-167AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2M X 36 CACHE SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 906K |
| 代理商： | CY7C1484V25-167AXI |
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CY7C1484V25
CY7C1485V25
Document #: 38-05286 Rev. *H
Page 7 of 26
tri-stated whenever a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BW
) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses need a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQ
X
is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation remain unaltered. A synchronous self-timed
write mechanism is provided to simplify the write operations.
Because the CY7C1484V25/CY7C1485V25 is a common IO
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ
X
inputs. Doing so tri-states
the output drivers. As a safety precaution, DQ
X
are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1484V25/CY7C1485V25 provides a two-bit
wraparound counter, fed by A
[1:0]
, that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected before entering the “sleep” mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
A1: A0
00
01
10
11
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
01
00
11
10
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
Min
Max
Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current
120
mA
Device operation to ZZ
2t
CYC
ns
ZZ recovery time
2t
CYC
ns
ZZ Active to sleep current
This parameter is sampled
2t
CYC
ns
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
[+] Feedback
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