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參數(shù)資料
| 型號(hào)： | CY7C1484V25-200AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2M X 36 CACHE SRAM, 3 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 18/26頁 |
| 文件大?。?/td> | 906K |
| 代理商： | CY7C1484V25-200AXC |
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CY7C1484V25
CY7C1485V25
Document #: 38-05286 Rev. *H
Page 18 of 26
Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when V
DDQ
= 2.5V and is 0.9V when V
DDQ
= 1.8V. Test conditions
shown in (a) of
“AC Test Loads and Waveforms” on page 17
unless otherwise noted.
Parameter
Description
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
t
POWER
Clock
V
DD
(Typical) to the First Access
[14]
1
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
4.0
5
6
ns
Clock HIGH
2.0
2.0
2.2
ns
Clock LOW
2.0
2.0
2.2
ns
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
Data Output Valid After CLK Rise
3.0
3.0
3.4
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[15, 16, 17]
Clock to High-Z
[15, 16, 17]
1.3
1.3
1.5
ns
1.3
1.3
1.5
ns
3.0
3.0
3.4
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[15, 16, 17]
OE HIGH to Output High-Z
[15, 16, 17]
3.0
3.0
3.4
ns
0
0
0
ns
3.0
3.0
3.4
ns
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
Address Setup Before CLK Rise
1.4
1.4
1.5
ns
ADSC, ADSP Setup Before CLK Rise
1.4
1.4
1.5
ns
ADV Setup Before CLK Rise
1.4
1.4
1.5
ns
GW, BWE, BW
X
Setup Before CLK Rise
Data Input Setup Before CLK Rise
1.4
1.4
1.5
ns
1.4
1.4
1.5
ns
Chip Enable Setup Before CLK Rise
1.4
1.4
1.5
ns
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Address Hold After CLK Rise
0.4
0.4
0.5
ns
ADSP, ADSC Hold After CLK Rise
0.4
0.4
0.5
ns
ADV Hold After CLK Rise
0.4
0.4
0.5
ns
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
0.4
0.4
0.5
ns
0.4
0.4
0.5
ns
Chip Enable Hold After CLK Rise
0.4
0.4
0.5
ns
Notes
14.This part has an internal voltage regulator; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
15.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of
“AC Test Loads and Waveforms” on page 17
. Transition is measured ±200 mV
from steady-state voltage.
16.At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
17.This parameter is sampled and not 100% tested.
[+] Feedback
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