- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379078 > CY7C1484V25 (Cypress Semiconductor Corp.) 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM PDF資料下載
參數(shù)資料
| 型號： | CY7C1484V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 72兆位（2米x 36/4M × 18）流水線雙氰胺同步靜態(tài)存儲器 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大小： | 906K |
| 代理商： | CY7C1484V25 |
CY7C1484V25
CY7C1485V25
Document #: 38-05286 Rev. *H
Page 5 of 26
Pin Definitions
Pin Name
IO
Description
A
0
, A
1
, A
Input-
Synchronous
Address Inputs used to select one of the address locations
. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A1:
A0 are fed to the two-bit counter.
BW
A
,BW
B
BW
C
,BW
D
GW
Input-
Synchronous
Byte Write Select Inputs, active LOW
. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Global Write Enable Input, active LOW
. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
X
and BWE).
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
BWE
Input-
Synchronous
CLK
Input-
Clock
Clock Input
. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW during a burst operation.
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
2
and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is
sampled only when a new external address is loaded.
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select or deselect the device. CE
2
is sampled only when a new external
address is loaded.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
2
to select or deselect the device. CE
3
is sampled only when a new external
address is loaded.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW
. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW
. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW
. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW
. When
asserted LOW, addresses presented to the device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ADSC
Input-
Synchronous
ZZ
Input-
Asynchronous
ZZ “sleep” Input, active HIGH
. When asserted HIGH, places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW
or left floating. ZZ pin has an internal pull down.
DQs, DQPs
IO-
Synchronous
Bidirectional Data IO lines
. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQP
X
are placed in a tri-state condition.
Power supply inputs to the core of the device
.
V
DD
V
SS
V
SSQ[2]
V
DDQ
Power Supply
Ground
Ground for the core of the device
.
IO Ground
Ground for the IO circuitry
.
IO Power Supply
Power supply for the IO circuitry
.
Note
2. Applicable for TQFP package. For BGA package V
SS
serves as ground for the core and the IO circuitry.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1484V25-200BZI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-200BZXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-200BZXI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-250AXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-250AXI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C149 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C149-45PC | 功能描述:1KX4 18-PIN SRAM RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C150-10DC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C150-15PC | 制造商:Rochester Electronics LLC 功能描述:4K (1K X 4)- 24 PIN 300 MIL SEPARATE I/O & RESET SRAM - Bulk |
| CY7C15025PC | 制造商:CYPRESS 功能描述:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。