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參數(shù)資料
| 型號： | CY7C1484V33-167AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2M X 36 CACHE SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 909K |
| 代理商： | CY7C1484V33-167AXI |
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72-Mbit (2M x 36/4M x 18) Pipelined
DCD Sync SRAM
CY7C1484V33
CY7C1485V33
Cypress Semiconductor Corporation
Document #: 38-05285 Rev. *G
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 01, 2007
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double cycle deselect)
Depth expansion without wait state
3.3V core power supply (V
DD
)
2.5V/3.3V IO operation
Fast clock-to-output times
— 3.0 ns (for 250 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
CY7C1484V33
,
CY7C1485V33
available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x
36/4M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle. This part supports byte write
operations (see
“Pin Definitions” on page 5
and
“Truth Table”
on page 8
for further details). Write cycles can be one to four
bytes wide as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written. This device incor-
porates an additional pipelined enable register which delays
turning off the output buffers an additional cycle when a
deselect is executed.This feature enables depth expansion
without penalizing system performance.
The CY7C1484V33/CY7C1485V33 operates from a +3.3V
core power supply while all outputs operate with a +3.3V or a
+2.5V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note
1. For best practices recommendations, please refer to the Cypress application note
AN1064, SRAM System Guidelines
.
Selection Guide
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1484V33-167BZI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V33-167BZXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V33-167BZXI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V33-200AXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V33-200AXI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
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