參數(shù)資料
型號(hào)： CY7C1485V25-250AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM
中文描述： 4M X 18 CACHE SRAM, 3 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù)： 11/26頁(yè)
文件大?。?/td> 906K
代理商： CY7C1485V25-250AXC
CY7C1484V25
CY7C1485V25
Document #: 38-05286 Rev. *H
Page 11 of 26
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the
“TAP Controller Block
Diagram” on page 10
. During power up, the instruction register
is loaded with the IDCODE instruction. It is also loaded with
the IDCODE instruction if the controller is placed in a reset
state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
enable fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
SS
) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register and the x18 configuration has a 54-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the IO ring.
The
Boundary Scan Order tables on page 14
show the order
in which the bits are connected. Each bit corresponds to one
of the bumps on the SRAM package. The MSB of the register
is connected to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in
“Identification Register Defini-
tions” on page 13
.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in
“Identification
Codes” on page 14
. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the IO
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-
IR state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction, which is to be
executed whenever the instruction register is loaded with all
zeros. EXTEST is not implemented in this SRAM TAP
controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-zero instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
at power up or whenever the TAP controller is in a test logic
reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, but the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (t
CS
plus t
CH
).
[+] Feedback
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