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參數(shù)資料
| 型號： | CY7C1485V25-250AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 4M X 18 CACHE SRAM, 3 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 906K |
| 代理商： | CY7C1485V25-250AXI |
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CY7C1484V25
CY7C1485V25
Document #: 38-05286 Rev. *H
Page 13 of 26
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
1.8V TAP AC Test Conditions
Input pulse levels..................................... 0.2V to V
DDQ
– 0.2
Input rise and fall time .....................................................1 ns
Input timing reference levels..............................................9V
Output reference levels ..................................................0.9V
Test load termination supply voltage ..............................0.9V
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
1.8V TAP AC Output Load Equivalent
TDO
0.9V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 2.5V ±0.125V unless otherwise noted)
[11]
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
OH1
V
OH2
Output HIGH Voltage
I
OH
= –1.0 mA
I
OH
= –100
μ
A
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
1.7
V
Output HIGH Voltage
2.1
V
1.6
V
V
OL1
V
OL2
Output LOW Voltage
I
OL
= 1.0 mA
I
OL
= 100
μ
A
0.4
V
Output LOW Voltage
0.2
V
0.2
V
V
IH
Input HIGH Voltage
1.7
V
DD
+ 0.3
V
DD
+ 0.3
0.7
V
1.26
V
V
IL
Input LOW Voltage
–0.3
V
–0.3
0.36
V
μ
A
I
X
Input Load Current
GND
≤
V
I
≤
V
DDQ
–5
5
Identification Register Definitions
Instruction Field
CY7C1484V25
(2M x 36)
CY7C1485V25
(4M x 18)
Description
Revision Number (31:29)
000
000
Describes the version number
Device Depth (28:24)
01011
01011
Reserved for internal use
Architecture/Memory Type(23:18)
000110
000110
Defines memory type and architecture
Bus Width/Density (17:12)
100100
010100
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Enables unique identification of SRAM vendor
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID register
Note
11. All voltages refer to V
SS
(GND).
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1485V25-250BZC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1485V25-250BZI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-167AXC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-167AXI | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
| CY7C1484V25-167BZC | 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
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| CY7C149 WAF | 制造商:Cypress Semiconductor 功能描述: |
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