參數(shù)資料
型號(hào)： CY7C1487V33-100BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
中文描述： 1M X 72 CACHE SRAM, 6.5 ns, PBGA209
封裝： 14 X 22 MM, 1.76 MM HEIGHT, PLASTIC, FBGA-209
文件頁(yè)數(shù)： 30/30頁(yè)
文件大?。?/td> 998K
代理商： CY7C1487V33-100BGI
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *H
Page 30 of 30
Document History Page
Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Document Number: 38-05284
Orig. of
Change
**
114671
08/12/02
PKS
New Data Sheet
*A
118283
01/27/03
HGK
Updated Ordering Information
Updated the features for package offering
Changed from Advance Information to Preliminary
*B
233368
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 150-MHz speed grade offering
Changed package outline for 165FBGA package and 209-ball BGA
package
Removed 119-BGA package offering
*C
299452
See ECN
SYT
Removed 117-MHz Speed Bin
Changed
Θ
JA
from 16.8 to 24.63
°
C/W and
Θ
JC
from 3.3 to 2.28
°
C/W for
100 TQFP Package on Page # 21
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the
Ordering Information
*D
323080
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified
as per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Modified V
OL,
V
OH
test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*E
416193
See ECN
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 19
Changed the I
X
current values of MODE on page # 19 from -5
μ
A and 30
μ
A
to -30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 19 from -30
μ
A and 5
μ
A
to -5
μ
A and 30
μ
A
Changed V
IH
< V
DD
to V
IH
< V
DD
on page # 19
Replaced Package Name column with Package Diagram in the Ordering
Information table
*F
470723
See ECN
VKN
Converted from Preliminary to Final
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP
AC Switching Characteristics table
Updated the Ordering Information table
*G
486690
See ECN
VKN
Corrected the typo in the 209-Ball FBGA pinout.
(Corrected the ball name H9 to V
SS
from V
SSQ
).
*H
1062041
See ECN
VKN/KKVTMP Added footnote #2 related to V
SSQ
REV.
ECN NO.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1487V33-100BGXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1487V33-100BGXI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1487V33-133BGI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1487V33-133BGXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1487V33-150BGC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
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