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參數(shù)資料
| 型號： | CY7C1487V33-133BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 6.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, PLASTIC, FBGA-209 |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 998K |
| 代理商： | CY7C1487V33-133BGI |
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *H
Page 9 of 30
All IOs are tri-stated when a write is detected, even a byte
write. Because this is a common IO device, the asynchronous
OE input signal must be deasserted and the IOs must be
tri-stated before the presentation of data to DQ
s
. As a safety
precaution, the data lines are tri-stated once a write cycle is
detected, regardless of the state of OE.
Burst Sequences
The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides
an on-chip two-bit wraparound burst counter inside the SRAM.
The burst counter is fed by A[1:0], and can follow either a linear
or interleaved burst order. The burst order is determined by the
state of the MODE input. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved
burst order. Leaving MODE unconnected causes the device to
default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed.
The device must be deselected before entering the “sleep”
mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
A1: A0
00
01
10
11
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
01
00
11
10
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
Min
Max
Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current
150
mA
Device operation to ZZ
2t
CYC
ns
ZZ recovery time
2t
CYC
ns
ZZ active to sleep current
This parameter is sampled
2t
CYC
ns
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1487V33-133BGXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| CY7C1487V33-150BGC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1487V33-133BGC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33 | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-100AC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
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