參數(shù)資料
型號(hào)： CY7C1487V33-150BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 2M x 36/4M x 18/1M x 72 Flow-through SRAM
中文描述： 1M X 72 STANDARD SRAM, 5.5 ns, PBGA209
封裝： 14 X 22 MM, 2.20 MM HEIGHT, PLASTIC, BGA-209
文件頁數(shù)： 20/30頁
文件大?。?/td> 638K
代理商： CY7C1487V33-150BGC
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 20 of 30
Capacitance
[14]
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= V
DDQ
= 3.3V
Max.
TBD
TBD
TBD
Unit
pF
pF
pF
C
IN
C
CLK
C
I/O
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Thermal Resistance
[14]
Parameter
Q
JA
Description
Test Conditions
BGA Typ.
TBD
TQFP Typ.
TBD
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
Q
JC
TBD
TBD
°
C/W
Switching Characteristics
Over the Operating Range
Parameter
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CDV
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
Shaded areas contain advance information.
Notes:
13. Input waveform should have a slew rate of > 2 V/ns.
14. Tested initially and after any design or process change that may affect these parameters.
15. Unless otherwise noted, test conditions assume signal transition time of 1.5ns, timing reference levels of 1.75V, input pulse levels of 0 to 3.3V, and output
loading of the specified I
/I
OH
and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. t
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Description
-150
-133
-117
-100
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
6.7
7.5
8.5
10
ns
MHz
ns
ns
150
133
117
100
2.5
2.5
2.5
2.5
2.8
2.8
3.0
3.0
Data Output Valid After CLK Rise
OE LOW to Output Valid
[14, 16, 18]
Data Output Hold After CLK Rise
Clock to High-Z
[14, 15, 16, 17, 18]
Clock to Low-Z
[14, 15, 16, 17, 18]
OE HIGH to Output High-Z
[15, 16, 18]
OE LOW to Output Low-Z
[15, 16, 18]
5.5
2.5
6.5
3.0
7.5
3.4
8.5
3.8
ns
ns
ns
ns
ns
ns
ns
2.5
2.5
2.5
2.5
3.5
3.8
4.0
4.5
2.5
3.0
3.0
3.0
2.5
3.0
3.5
4
0
0
0
0
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
ns
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.5 for 3.3V V
DDQ
= 1.25 for 2.5V V
DDQ
V
DDQ
ALL INPUT PULSES
[13]
Vdd
GND
90%
10%
90%
10%
Rise Time:
2 V/ns
(c)
Fall Time:
2 V/ns
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