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參數(shù)資料
| 型號： | CY7C1510AV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 1074K |
| 代理商： | CY7C1510AV18-167BZC |
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PRELIMINARY
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Document #: 001-06984 Rev. *B
Page 10 of 26
Write Cycle Descriptions
(CY7C1510AV18 and CY7C1512AV18)
[3, 9]
BWS
0
/NWS
0
L
BWS
1
/NWS
1
L
K
K
Comments
L-H
–
During the Data portion of a Write sequence
:
CY7C1510AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1512AV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1510AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1512AV18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1510AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1512AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
L
L
–
L
H
L-H
L
H
–
L-H During the Data portion of a Write sequence
:
CY7C1510AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1512AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
H
L
L-H
–
During the Data portion of a Write sequence
:
CY7C1510AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1512AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
H
L
–
L-H During the Data portion of a Write sequence
:
CY7C1510AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1512AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
H
H
L-H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L-H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
(CY7C1525AV18)
BWS
0
L
K
K
Comments
L-H
–
During the Data portion of a Write sequence
:
CY7C1525AV18
the single byte (D
[8:0]
) is written into the device
During the Data portion of a Write sequence
:
CY7C1525AV18
the single byte (D
[8:0]
) is written into the device
No data is written into the devices during this portion of a write operation.
L
–
L-H
H
L-H
–
H
–
L-H
No data is written into the devices during this portion of a write operation.
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0,
NWS
1,
BWS
0
,BWS
1
,BWS
2
and BWS
3
can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1510AV18-167BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-167BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-167BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-200BZC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-200BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C15121TC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C15121YC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C15121YC-GBBC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1512-20VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1512-25SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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