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參數(shù)資料
| 型號： | CY7C1510AV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 16/26頁 |
| 文件大?。?/td> | 1074K |
| 代理商： | CY7C1510AV18-167BZC |
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Document #: 001-06984 Rev. *B
Page 16 of 26
TAP AC Switching Characteristics
Over the Operating Range
[12, 13]
TAP Timing and Test Conditions
[13]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times5
t
TMSH
t
TDIH
t
CH
Output Times
t
TDOV
t
TDOX
Description
Min.
50
Max.
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
20
20
20
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
Notes:
12.t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
13.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
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| CY7C1510AV18-167BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-167BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-167BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-200BZC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
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| CY7C15121TC | 制造商:Cypress Semiconductor 功能描述: |
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| CY7C1512-25SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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