參數(shù)資料
型號(hào)： CY7C1510AV18-167BZC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
中文描述： 8M X 8 QDR SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 17/26頁(yè)
文件大?。?/td> 1074K
代理商： CY7C1510AV18-167BZC
PRELIMINARY
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Document #: 001-06984 Rev. *B
Page 17 of 26
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
Value
Description
Version
number.
CY7C1510AV18
001
CY7C1525AV18
001
CY7C1512AV18
001
CY7C1514AV18
001
11010011010000100 11010011010001100 11010011010010100 11010011010100100 Defines the
type of SRAM.
Unique identifi-
cation of SRAM
vendor.
Indicates the
presence of an
ID register.
00000110100
00000110100
00000110100
00000110100
ID Register Presence
(0)
1
1
1
1
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan Cells
Bit Size
3
1
32
109
Instruction Codes
Instruction
Code
000
001
Description
EXTEST
IDCODE
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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CY7C1510AV18-167BZI 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
CY7C1510AV18-167BZXC 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
CY7C1510AV18-167BZXI 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
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