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參數(shù)資料
| 型號： | CY7C1510AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 72兆位QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 1074K |
| 代理商： | CY7C1510AV18 |
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PRELIMINARY
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Document #: 001-06984 Rev. *B
Page 22 of 26
Hold Times
t
HA
t
HC
t
HCDDR
t
KHAX
t
KHIX
t
KHIX
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS) 0.35
Double Data Rate Control Hold after Clock
(K/K) Rise (BWS
0
, BWS
1
, BWS
3
, BWS
4
)
D
[X:0]
Hold after Clock (K/K) Rise
0.35
–
–
–
0.4
0.4
0.4
–
–
–
0.5
0.5
0.5
–
–
–
ns
ns
ns
0.35
t
HD
Output Times
t
CO
t
KHDX
0.35
–
0.4
–
0.5
–
ns
t
CHQV
C/C Clock Rise (or K/K in Single Clock
Mode) to Data Valid
Data Output Hold after Output C/C Clock
Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
[26]
CQ Clock Rise to CQ Clock Rise
[26]
(rising edge to rising edge)
Clock (C/C) Rise to High-Z (Active to
High-Z)
[27, 28]
Clock (C/ C) Rise to Low-Z
[27, 28]
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
-0.45
–
-0.50
–
ns
t
CCQO
t
CQOH
t
CQD
t
CQDOH
t
CQH
t
CQHCQH
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHQX
t
CQHCQL
t
CQHCQH
–
0.45
–
0.30
–
–
–
–
0.45
–
0.35
–
–
–
–
0.50
–
0.40
–
–
–
ns
ns
ns
ns
ns
ns
–0.45
–
-0.30
1.55
1.55
-0.45
–
-0.35
1.95
1.95
-0.50
–
-0.40
2.45
2.45
t
CHZ
t
CHQZ
–
0.45
–
0.45
–
0.50
ns
t
CLZ
DLL Timing
t
KC Var
t
KC lock
t
KC Reset
Notes:
26.These parameters are extrapolated from the input timing parameters (t
- 250ps, where 250ps is the internal jitter. An input jitter of 200ps (t
KC Var
) ia already
included in the t
). These parameters are only guaranteed by design and are not tested in production.
27.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
28.At any given voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
t
CHQX1
-0.45
–
-0.45
–
-0.50
–
ns
t
KC Var
t
KC lock
t
KC Reset
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
–
0.20
–
–
–
0.20
–
–
–
0.20
–
–
ns
1024
30
1024
30
1024
30
Cycles
ns
Switching Characteristics
Over the Operating Range
[22, 23]
Cypress
Parameter
Consortium
Parameter
Description
250 MHz
Min.
200 MHz
Min.
167 MHz
Min.
Unit
Max
Max
Max
[+] Feedback
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