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參數(shù)資料
| 型號： | CY7C1510V18-167BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 17/27頁 |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C1510V18-167BZXC |
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CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 17 of 27
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
Value
Description
Version
number.
CY7C1510V18
000
CY7C1525V18
000
CY7C1512V18
000
CY7C1514V18
000
11010011010000100 11010011010001100 11010011010010100 11010011010100100 Defines the
type of SRAM.
Unique identifi-
cation of SRAM
vendor.
Indicates the
presence of an
ID register.
00000110100
00000110100
00000110100
00000110100
ID Register Presence
(0)
1
1
1
1
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan Cells
Bit Size
3
1
32
109
Instruction Codes
Instruction
Code
Description
EXTEST
IDCODE
000
001
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1510V18-167BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510V18-200BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510V18-200BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510V18-200BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510V18-250BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C15121TC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C15121YC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C15121YC-GBBC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1512-20VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1512-25SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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