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參數(shù)資料
| 型號： | CY7C1510V18-300BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 10/27頁 |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C1510V18-300BZI |
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CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 10 of 27
Write Cycle Descriptions
(CY7C1510V18 and CY7C1512V18)
[3, 9]
BWS
0
/
NWS
0
L
BWS
1
/
NWS
1
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1510V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1512V18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1510V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1512V18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1510V18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1512V18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
L
L
–
L
H
L-H
L
H
–
L-H During the Data portion of a Write sequence
:
CY7C1510V18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1512V18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
H
L
L-H
–
During the Data portion of a Write sequence
:
CY7C1510V18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1512V18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
H
L
–
L-H During the Data portion of a Write sequence
:
CY7C1510V18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1512V18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
H
H
L-H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L-H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
(CY7C1514V18)
[3, 9]
BWS
0
BWS
1
L
BWS
2
L
BWS
3
L
K
K
-
Comments
L
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
L
L
L
L
-
L-H During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
L
H
H
H
L-H
-
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
-
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
will remain unaltered.
L
H
H
H
-
H
L
H
H
L-H
H
L
H
H
-
H
H
L
H
L-H
H
H
L
H
-
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0,
NWS
1,
BWS
0
,BWS
1
,BWS
2
and BWS
3
can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
[+] Feedback
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| CY7C1510V18-300BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
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