參數(shù)資料
型號(hào): CY7C1510V18-300BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
中文描述: 8M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 11/27頁
文件大?。?/td> 458K
代理商: CY7C1510V18-300BZI
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 11 of 27
H
H
H
L
L-H
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
will remain unaltered.
-
No data is written into the device during this portion of a write operation.
H
H
H
L
-
H
H
H
H
L-H
H
H
H
H
-
L-H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
(CY7C1525V18)
BWS
0
L
K
K
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1525V18
the single byte (D
[8:0]
) is written into the device
During the Data portion of a Write sequence
:
CY7C1525V18
the single byte (D
[8:0]
) is written into the device,
No data is written into the devices during this portion of a write operation.
L
L-H
H
L-H
H
L-H
No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
(CY7C1514V18) (continued)
[3, 9]
BWS
0
BWS
1
BWS
2
BWS
3
K
K
Comments
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CY7C1510V18-300BZXC 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
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