參數(shù)資料
型號(hào)： CY7C1510V18-300BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
中文描述： 8M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 20/27頁
文件大?。?/td> 458K
代理商： CY7C1510V18-300BZI
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 20 of 27
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +2.9V
Supply Voltage on V
DDQ
Relative to GND ......–0.5V to +V
DD
DC Voltage Applied to Outputs
in High-Z State.................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage
[19]
...............................–0.5V to V
DD
+ 0.5V
Electrical Characteristics
Over the Operating Range
[16, 19]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature (T
A
)
0°C to +70°C
–40°C to +85°C
V
DD
[20]
1.8
±
0.1V
V
DDQ
[20]
1.4V to V
DD
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
V
DD
Power Supply Voltage
V
DDQ
I/O Supply Voltage
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
V
OH(LOW)
Output HIGH Voltage
V
OL(LOW)
Output LOW Voltage
V
IH
V
IL
I
X
Input Leakage Current
I
OZ
Output Leakage Current
V
REF[21]
I
DD
V
DD
Operating Supply
Test Conditions
Min.
1.7
1.4
Typ.
1.8
1.5
Max.
1.9
V
DD
Unit
V
V
V
V
V
V
V
V
μ
A
μ
A
V
mA
mA
mA
mA
mA
mA
Note 17
Note 18
I
OH
=
0.1 mA, Nominal Impedance
I
OL
= 0.1 mA, Nominal Impedance
V
DDQ
/2 – 0.12
V
DDQ
/2 – 0.12
V
DDQ
– 0.2
V
SS
V
REF
+ 0.1
–0.3
5
5
0.68
V
DDQ
/2 + 0.12
V
DDQ
/2 + 0.12
V
DDQ
0.2
V
DDQ
+ 0.3
V
REF
– 0.1
5
5
0.95
800
850
950
360
380
400
Input HIGH Voltage
[19]
Input LOW Voltage
[19,13]
GND
≤
V
I
≤
V
DDQ
GND
≤
V
I
≤
V
DDQ,
Output Disabled
Input Reference Voltage
[15]
Typical Value = 0.75V
0.75
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
167 MHz
200 MHz
250 MHz
167 MHz
200 MHz
250 MHz
I
SB1
Automatic Power-down
Current
Max. V
DD
, Both Ports
Deselected, V
IN
≥
V
IH
or
V
IN
≤
V
IL
f = f
MAX
=
1/t
CYC,
Inputs Static
AC Input Requirements
Over the Operating Range
Parameter
V
IH
V
IL
Description
Test Conditions
Min.
Typ.
–
–
Max.
–
Unit
V
V
Input HIGH Voltage
Input LOW Voltage
V
REF
+ 0.2
–
V
REF
- 0.2
Capacitance
[22]
Parameter
C
IN
C
CLK
C
O
Notes:
16.All voltage referenced to Ground.
17.Output are impedance controlled. I
OH
= –(V
DDQ
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
18.Output are impedance controlled. I
= (V
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
19.Overshoot: V
(AC) < V
+ 0.85V (Pulse width less than t
/2), Undershoot: V
(AC) > -1.5V (Pulse width less than t
CYC
/2).
20.Power-up: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time V
< V
and V
< V
DD
.
21.V
(min.) = 0.68V or 0.46V
, whichever is larger, V
(max.) = 0.95V or 0.54V
, whichever is smaller.
22.Tested initially and after any design or process change that may affect these parameters.
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 1.8V
V
DDQ
= 1.5V
Max.
5.5
8.5
8
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Output Capacitance
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