參數(shù)資料
型號(hào)： CY7C1510V18-300BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
中文描述： 8M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 458K
代理商： CY7C1510V18-300BZI
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 7 of 27
Functional Overview
The
CY7C1514V18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read Port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1510V18, two 9-bit data transfers in the case of
CY7C1525V18, two 18-bit data transfers in the case of
CY7C1512V18 and two 36-bit data transfers in the case of
CY7C1514V18, in one clock cycle.
CY7C1510V18,CY7C1525V18,CY7C1512V18
and
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D
[x:0]
) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q
[x:0]
) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS
[x:0]
) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1512V18 is described in the following sections. The
same
basic
descriptions
CY7C1525V18 and CY7C1514V18.
apply
to
CY7C1510V18,
K
Input-Clock
Positive Input Clock Input
. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
[x:0]
when in single clock mode. All accesses
are initiated on the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
[x:0]
when in single clock mode.
CQ is referenced with respect to C
. This is a free running clock and is synchronized
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC timing
table.
K
Input-Clock
CQ
Echo Clock
CQ
Echo Clock
CQ is referenced with respect to C
. This is a free running clock and is synchronized
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC timing
table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the
system data bus impedance. CQ,CQ and Q
[x:0]
output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
DDQ
, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
DLL Turn Off - Active LOW
. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet.
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Not connected to the die
. Can be tied to any voltage level.
Address expansion for 144M
. Can be tied to any voltage level.
Address expansion for 288M
. Can be tied to any voltage level.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device
.
Ground for the device
.
Power supply inputs for the outputs of the device
.
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
V
SS
/144M
V
SS
/288M
V
REF
Output
Input
Input
Input
N/A
Input
Input
Input-
Reference
Power Supply
Ground
Power Supply
V
DD
V
SS
V
DDQ
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1510V18-300BZXC 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
CY7C1510V18-300BZXI 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
CY7C1512V18-167BZI 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
CY7C1512V18-167BZXC 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
CY7C1512V18-167BZXI 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C15121TC 制造商:Cypress Semiconductor 功能描述:
CY7C15121YC 制造商:Cypress Semiconductor 功能描述:
CY7C15121YC-GBBC 制造商:Cypress Semiconductor 功能描述:
CY7C1512-20VC 制造商:Cypress Semiconductor 功能描述:
CY7C1512-25SC 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*