- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379083 > CY7C1510V18-300BZI (CYPRESS SEMICONDUCTOR CORP) 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1510V18-300BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C1510V18-300BZI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 9 of 27
Application Example
[2]
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation
K
RPS
X
WPS
L
DQ
DQ
Write Cycle:
Load address on the rising edge of K clock;
input write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock;
wait one and a half cycle; read data on C
and C rising edges.
NOP: No Operation
L-H
D(A + 0) at K(t)
↑
D(A + 1) at K(t)
↑
L-H
L
X
Q(A + 0) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
L-H
H
H
D = X
Q = High-Z
Previous State
D = X
Q = High-Z
Previous State
Standby: Clock Stopped
Stopped
X
X
Notes:
2. The above application shows four QDR-II being used.
3. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
↑
represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
C
C#
D
A
K
C
C#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
οημσ
R = 250
οημσ
R = 250
οημσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1510V18-300BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510V18-300BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1512V18-167BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1512V18-167BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1512V18-167BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C15121TC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C15121YC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C15121YC-GBBC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1512-20VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1512-25SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。