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參數(shù)資料
| 型號(hào)： | CY7C1511V18-250BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 426K |
| 代理商： | CY7C1511V18-250BZI |
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CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 21 of 28
Capacitance
[24]
Parameter
C
IN
C
CLK
C
O
Thermal Resistance
[24]
Description
Test Conditions
Max.
5.5
8.5
8
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Output Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 1.8V
V
DDQ
= 1.5V
Parameter
Θ
JA
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
FBGA
16.2
Unit
°C/W
Test conditions follow standard test methods and procedures for
measuring thermal impedance, per EIA/JESD51.
Θ
JC
2.3
°C/W
AC Test Loads and Waveforms
Notes:
24.Tested initially and after any design or process change that may affect these parameters.
25.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250
, V
DDQ
= 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of AC test loads.
1.25V
0.25V
R = 50
5 pF
ALL INPUT PULSES
Device
Under
Test
R
L
= 50
Z
0
= 50
V
REF
= 0.75V
V
REF
= 0.75V
[25]
0.75V
0.75V
Device
Under
Test
OUTPUT
0.75V
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
(b)
RQ =
250
[+] Feedback
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