參數(shù)資料
型號(hào)： CY7C1511V18-250BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture
中文描述： 8M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 19/28頁(yè)
文件大?。?/td> 426K
代理商： CY7C1511V18-250BZXC
CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 19 of 28
Power-Up Sequence in QDR-II SRAM
[16, 17]
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
— Apply V
DD
before V
DDQ
— Apply V
DDQ
before V
REF
or at the same time as V
REF
After the power and clock (K, K, C, C) are stable take DOFF
HIGH
The additional 1024 cycles of clocks are required for the
DLL to lock
DLL Constraints
DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
t
KC Var
The DLL will function at frequencies down to 80MHz
If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
Notes:
16.It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1Kohm.
17.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Power-up Waveforms
> 1024 Stable clock
Start Normal
Operation
DOFF
Stabl
e
(< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
V
DD
V
/
DDQ
DD
V
V
/
Clock Start
(
Clock Starts after DD
)
V
/
~
~
~
~
Unstable Clock
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1511V18-250BZXI 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture
CY7C1511V18-278BZC 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture
CY7C1511V18-278BZI 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture
CY7C1511V18-278BZXC 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture
CY7C1511V18-278BZXI 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture
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