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參數(shù)資料
| 型號： | CY7C1511V18-250BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 426K |
| 代理商： | CY7C1511V18-250BZXC |
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CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 6 of 28
Pin Definitions
Pin Name
D
[x:0]
I/O
Input-
Pin Description
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations
.
CY7C1511V18
D
[7:0]
CY7C1526V18
D
[8:0]
CY7C1513V18
D
[17:0]
CY7C1515V18
D
[35:0]
Write Port Select, active LOW
. Sampled on the rising edge of the K clock. When asserted active,
a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D
[x:0]
to be ignored.
Nibble Write Select 0, 1
active LOW
.(
CY7C1511V18
Only
) Sampled on the rising edge of the
K and K clocks during write operations. Used to select which nibble is written into the device NWS
0
controls D
[3:0]
and NWS
1
controls D
[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select will cause the corresponding nibble of data to be ignored and not written into the device.
Byte Write Select 0, 1, 2 and 3
active LOW
. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1526V18
BWS
0
controls D
[8:0]
CY7C1513V18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1515V18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs
. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both Read and Write operations. Internally, the device is
organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1511V18, 8M x 9 (4 arrays each of 2M x
9) for CY7C1526V18,4M x 18 (4 arrays each of 1M x 18) for CY7C1513V18 and 2M x 36 (4 arrays
each of 512K x 36) for CY7C1515V18. Therefore, only 21 address inputs are needed to access
the entire memory array of CY7C1511V18 and CY7C1526V18, 20 address inputs for
CY7C1513V18 and 19 address inputs for CY7C1515V18.These inputs are ignored when the
appropriate port is deselected.
Data Output signals
. These pins drive out the requested data during a Read operation. Valid data
is driven out on the rising edge of both the C and C clocks during Read operations or K and K.
when in single clock mode. When the Read port is deselected, Q
[x:0]
are automatically tri-stated.
CY7C1511V18
Q
[7:0]
CY7C1526V18
Q
[8:0]
CY7C1513V18
Q
[17:0]
CY7C1515V18
Q
[35:0]
Read Port Select, active LOW
. Sampled on the rising edge of Positive Input Clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each read access consists of a burst of four
sequential transfers.
Positive Input Clock for Output Data
. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board back to the controller. See application example for further details.
Negative Input Clock for Output Data
. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board back to the controller. See application example for further details.
WPS
Input-
Synchronous
NWS
0
,NWS
1
Input-
Synchronous
BWS
0
,
BWS
1
,
BWS
2
, BWS
3
Input-
Synchronous
A
Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS
Input-
Synchronous
C
Input-
Clock
C
Input-
Clock
K
Input-
Clock
Positive Input Clock Input
. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
[x:0]
when in single clock mode.
K
Input-
Clock
[+] Feedback
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