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參數(shù)資料
| 型號： | CY7C1512AV18-250BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 4M X 18 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 1074K |
| 代理商： | CY7C1512AV18-250BZC |
PRELIMINARY
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Document #: 001-06984 Rev. *B
Page 19 of 26
Power-up Sequence in QDR-II SRAM
[14]
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
— Apply V
DD
before V
DDQ
— Apply V
DDQ
before V
REF
or at the same time as V
REF
Provide stable power and clock (K, K) for 1024 cycles to
lock the DLL.
Power-up Waveforms
DLL Constraints
DLL uses K clock as its synchronizing input. The input
should have low phase jitter, which is specified as t
KC Var
.
The DLL will function at frequencies down to 80 MHz.
If the input clock is unstable and the DLL is enabled, then
the DLL may lock onto an incorrect frequency, causing
unstable SRAM behavior. To avoid this, provide 1024 cycles
stable clock to relock to the desired clock frequency
Notes:
14.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
> 1024 Stable clock
Start Normal
Operation
DOFF
Stabl
e
(< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
V
DD
V
/
DDQ
DD
V
V
/
Clock Start
(
Clock Starts after DD
)
V
/
~
~
~
~
Unstable Clock
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1512AV18-250BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1512AV18-250BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1512AV18-250BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1514AV18 | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1514AV18-167BZC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1512AV18-250BZI | 功能描述:靜態(tài)隨機存取存儲器 4Mx18 72M QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1512AV18-250BZIT | 功能描述:靜態(tài)隨機存取存儲器 4Mx18 72M QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1512AV18-250BZXC | 功能描述:靜態(tài)隨機存取存儲器 4Mx18 72M QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1512AV18-250BZXI | 功能描述:靜態(tài)隨機存取存儲器 4Mx18 72M QDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1512AV18-250BZXIT | 功能描述:靜態(tài)隨機存取存儲器 4Mx18 72M QDR-II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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