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| 型號： | CY7C1515V18-300BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| 中文描述： | 2M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 426K |
| 代理商： | CY7C1515V18-300BZXC |
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CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 22 of 28
Switching Characteristics
Over the Operating Range
[25, 26]
Cypress
Parameter
t
POWER
Consortium
Parameter
Description
300 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
1
1
278 MHz
250 MHz
200 MHz
167 MHz
Unit
ms
V
DD
(Typical) to the first
Access
[29]
K Clock and C Clock Cycle
Time
Input Clock (K/K; C/C) HIGH 1.32
Input Clock (K/K; C/C) LOW
1
1
t
CYC
t
KHKH
3.30 5.25 3.60 5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KL
t
KHKH
t
KHKL
t
KLKH
t
KHKH
–
–
–
1.4
1.4
1.6
–
–
–
1.6
1.6
1.8
–
–
–
2.0
2.0
2.2
2.4
2.4
2.7
–
–
–
ns
ns
ns
1.32
1.49
–
–
K Clock Rise to K Clock Rise
and C to C Rise
(rising edge to rising edge)
K/K Clock Rise to C/C Clock
Rise
(rising edge to rising edge)
t
KHCH
t
KHCH
0.0
1.45
0.0
1.55
0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K Clock
Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
Control Set-up to Clock
(K, K, C, C) Rise (RPS, WPS)
Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS
0
, BWS
1,
BWS
2
, BWS
3
)
D
[X:0]
Set-up to Clock (K/K)
Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[30]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after Clock
(K/K) Rise
Control Hold after Clock (K
K) Rise (RPS, WPS)
Double Data Rate Control
Hold after Clock (K/K) Rise
(BWS
0
, BWS
1,
BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock (K/K)
Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
Data Output Hold after Output
C/C Clock Rise
(Active to Active)
C/C Clock Rise to Echo Clock
Valid
Echo Clock Hold after C/C
Clock Rise
0.45
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CCQO
t
CHCQV
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
CQOH
t
CHCQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
Notes:
26.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
27.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
28.At any given voltage and temperature t
is less than t
and t
less than t
.
29.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
30.For D0 data signal on CY7C1526V18 device, t
SD
is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1515V18-300BZXI | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| CY7C1526V18-167BZI | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| CY7C1526V18-167BZXC | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| CY7C1526V18-167BZXI | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| CY7C1526V18-200BZI | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1515ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1518-250BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1518AV18-167BZC | 功能描述:靜態(tài)隨機存取存儲器 4M x 18 1.8V DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1518AV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 4M x 18 1.8V DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1518AV18-250BZI | 功能描述:靜態(tài)隨機存取存儲器 4M x 18 1.8V DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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