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參數(shù)資料
| 型號(hào)： | CY7C1525AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 72兆位QDR - II型⑩SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 1074K |
| 代理商： | CY7C1525AV18 |
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PRELIMINARY
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Document #: 001-06984 Rev. *B
Page 10 of 26
Write Cycle Descriptions
(CY7C1510AV18 and CY7C1512AV18)
[3, 9]
BWS
0
/NWS
0
L
BWS
1
/NWS
1
L
K
K
Comments
L-H
–
During the Data portion of a Write sequence
:
CY7C1510AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1512AV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1510AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1512AV18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1510AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1512AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
L
L
–
L
H
L-H
L
H
–
L-H During the Data portion of a Write sequence
:
CY7C1510AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1512AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
H
L
L-H
–
During the Data portion of a Write sequence
:
CY7C1510AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1512AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
H
L
–
L-H During the Data portion of a Write sequence
:
CY7C1510AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1512AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
H
H
L-H
–
No data is written into the devices during this portion of a write operation.
H
H
–
L-H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
(CY7C1525AV18)
BWS
0
L
K
K
Comments
L-H
–
During the Data portion of a Write sequence
:
CY7C1525AV18
the single byte (D
[8:0]
) is written into the device
During the Data portion of a Write sequence
:
CY7C1525AV18
the single byte (D
[8:0]
) is written into the device
No data is written into the devices during this portion of a write operation.
L
–
L-H
H
L-H
–
H
–
L-H
No data is written into the devices during this portion of a write operation.
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0,
NWS
1,
BWS
0
,BWS
1
,BWS
2
and BWS
3
can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1525AV18-167BZC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1525AV18-167BZI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1525AV18-167BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1525AV18-167BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1510AV18-167BZC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1525JV18250BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1525JV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M x 9 1.8V QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525JV18-250BZCES | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1525JV18-250BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M x 9 1.8V QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525KV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (8Mx9) 1.8v 250MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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