- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379084 > CY7C1525V18-167BZI (CYPRESS SEMICONDUCTOR CORP) 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1525V18-167BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| 中文描述： | 8M X 9 QDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C1525V18-167BZI |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
72-Mbit QDR-II SRAM 2-Word Burst
Architecture
CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Cypress Semiconductor Corporation
Document #: 38-05489 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 31, 2006
Features
Separate Independent Read and Write Data Ports
— Supports concurrent transactions
250-MHz clock for high bandwidth
2-Word Burst on all accesses
Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
Echo clocks (CQ and CQ) simplify data capture in high
speed systems
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
Available in x8, x9, x18, and x36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8V (±0.1V); I/O V
DDQ
= 1.4V to V
DD
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in lead-free and non-lead free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1510V18 – 8M x 8
CY7C1525V18 – 8M x 9
CY7C1512V18 – 4M x 18
CY7C1514V18 – 2M x 36
Functional Description
The CY7C1510V18, CY7C1525V18, CY7C1512V18, and
CY7C1514V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another. In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with two 8-bit words
(CY7C1510V18) or 9-bit words (CY7C1525V18) or 18-bit
words (CY7C1512V18) or 36-bit words (CY7C1514V18) that
burst sequentially into or out of the device. Since data can be
transferred into and out of the device on every rising edge of
both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
250 MHz
250
950
200 MHz
200
850
167 MHz
167
800
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1525V18-167BZXC | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1525V18-167BZXI | 72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture |
| CY7C1516AV18 | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1516AV18-167BZC | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1516AV18-167BZI | 72-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1525V18-200BZC | 功能描述:靜態(tài)隨機存取存儲器 8M x 9 1.8V QDR II 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525V18-200BZXC | 功能描述:靜態(tài)隨機存取存儲器 8M x 9 1.8V QDR II 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525V18-250BZXC | 功能描述:IC SRAM 72MBIT 250MHZ 165LFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1526K | 制造商:Cypress Semiconductor 功能描述:FOR REG PURPOSE ONLY - Trays |
| CY7C1526KV18-300BZXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (8Mx9) 1.8v 300MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。