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參數(shù)資料
| 型號： | CY7C1526V18-200BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| 中文描述： | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 426K |
| 代理商： | CY7C1526V18-200BZXC |
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CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 10 of 28
Write Cycle Descriptions
CY7C1511V18 and CY7C1513V18)
[3, 11]
BWS
0
/
NWS
0
BWS
1
/
NWS
1
L
K
K
–
Comments
L
L–H
During the Data portion of a Write sequence
:
CY7C1511V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1513V18
both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence
:
CY7C1511V18
both nibbles (D
[7:0]
) are written into the device,
CY7C1513V18
both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence
:
CY7C1511V18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1513V18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1511V18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1513V18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1511V18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1513V18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1511V18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1513V18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
No data is written into the devices during this portion of a write operation.
No data is written into the devices during this portion of a write operation.
L
L
–
L-H
L
H
L–H
–
L
H
–
L–H
H
L
L–H
–
H
L
–
L–H
H
H
H
H
L–H
–
–
L–H
Note:
11. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table.NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
[+] Feedback
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