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參數(shù)資料
| 型號(hào)： | CY7C1526V18-278BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR⑩- II SRAM 4-Word Burst Architecture |
| 中文描述： | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 9/28頁(yè) |
| 文件大?。?/td> | 426K |
| 代理商： | CY7C1526V18-278BZC |
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CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Document #: 38-05363 Rev. *D
Page 9 of 28
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
Application Example
[2]
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
Truth Table
[3, 4, 5, 6, 7, 8]
Operation
Write Cycle:
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
Read Cycle:
Load address on the
rising edge of K; wait
one and a half cycle;
read data on two
consecutive C and C
rising edges.
NOP: No Operation
K
RPS WPS
H
[9]
DQ
DQ
DQ
DQ
L-H
L
[10]
D(A) at K(t + 1)
↑
D(A + 1) at K(t + 1)
↑
D(A + 2) at K(t + 2)
↑
D(A + 3) at K(t + 2)
↑
L-H
L
[10]
X
Q(A) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
Q(A + 2) at C(t + 2)
↑
Q(A + 3) at C(t + 3)
↑
L-H
H
H
D = X
Q = High-Z
Previous State
D = X
Q = High-Z
Previous State
D = X
Q = High-Z
Previous State
D = X
Q = High-Z
Previous State
Standby: Clock
Stopped
Stopped X
X
Notes:
2. The above application shows four QDR-II being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10.This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
Vt = Vddq/2
C C#
D
A
K
C C#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
ohms
R = 250
ohms
R = 250
ohms
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
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