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參數(shù)資料
| 型號(hào)： | CY7C43622 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256 x36 x2 Bidirectional Synchronous FIFO(256 x36 x2 雙向同步先進(jìn)先出) |
| 中文描述： | 256 x36 x2雙向同步FIFO（256 x36 x2雙向同步先進(jìn)先出） |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 463K |
| 代理商： | CY7C43622 |
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CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
7
PRELIMINARY
AC Test Loads and Waveforms (-10 & -15)
AC Test Loads and Waveforms ( -7)
Switching Characteristics
Over the Operating Range
Parameter
Description
CY7C43622/
32/42/62/82
-7
Min.
CY7C43622/
32/42/62/82
-10
Min.
CY7C43622/
32/42/62/82
-15
Min.
Unit
Max.
Max.
Max.
f
S
Clock Frequency, CLKA or CLKB
133
100
67
MH
z
t
CLK
t
CLKH
t
CLKL
t
DS
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
Pulse Duration, CLKA or CLKB LOW
Set-Up Time, A
0
–
35
before CLKA
↑
and B
0
–
35
before
CLKB
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA
↑
; CSB, W/RB, ENB, and MBB before CLKB
↑
Set-Up Time, RST1 or RST2 LOW before CLKA
↑
or
CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before RST1 and RST2
HIGH
3.5
4
6
ns
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
5
7
7.5
ns
t
BES
Set-Up Time, FWFT/STAN before RST1 and RST2
HIGH
Set-Up Time, FS0 before CLKA
↑
Set-Up Time, FS1 before CLKA
↑
Set-Up Time, FWFT before CLKA
↑
Hold Time, A
0
–
35
after CLKA
↑
and B
0
–
35
after
CLKB
↑
5
7
7.5
ns
t
SDS
t
SENS
t
FWS
t
DH
3
4
5
ns
3
4
5
ns
0
0
0
ns
0
0
0
ns
Note:
7.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
5V
OUTPUT
R2=680
C
L
=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
R1=1.1k
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
I/O
50
V
CC
/2
Z0=50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43682 | 16K x36 x2 Bidirectional Synchronous FIFO(16K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43633 | 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43623 | 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43643 | 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43663 | 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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