參數(shù)資料
型號: CY7C43633
廠商: Cypress Semiconductor Corp.
英文描述: 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進先出帶總線匹配)
中文描述: 512 x36單向同步FIFO瓦特/總線匹配(512 x36單向同步先進先出帶總線匹配)
文件頁數(shù): 13/28頁
文件大?。?/td> 422K
代理商: CY7C43633
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
13
PRELIMINARY
Notes:
20. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
21. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
CLK
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
Old Data in FIFO Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW1[21]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A
0
35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B
0
35
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
[20]
相關(guān)PDF資料
PDF描述
CY7C43623 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進先出帶總線匹配)
CY7C43643 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進先出帶總線匹配)
CY7C43663 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進先出帶總線匹配)
CY7C43683 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進先出帶總線匹配)
CY7C43634 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進先出 帶總線匹配)
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