參數(shù)資料
型號: CY7C43636
廠商: Cypress Semiconductor Corp.
英文描述: 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進先出)
中文描述: 512 x36/x18x2三總線的FIFO(512 x36/x18x2三路總線先進先出)
文件頁數(shù): 13/40頁
文件大?。?/td> 577K
代理商: CY7C43636
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
13
PRELIMINARY
Notes:
17. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
18. t
is the minimum time between the rising CLKA edge and a rising CLKB for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than t
SKEW1
, then FFC/IRC may transition HIGH one cycle later than shown.
Switching Waveforms
(continued)
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
t
WFF
t
FSS
t
DS
t
FSS
t
FSH
t
FSH
t
ENS
t
ENH
t
DH
t
SKEW1[18]
AFA Offset (Y1)
AFC Offset (Y2)
First Word to FIFO1
CLKA
MRS1, MRS2
SPM
FS1/SEN,
FS0/SD
FFA/IRA
ENA
A
0
35
CLKB
FFC/IRC
[17]
AEB Offset (X1)
AEA Offset (X2)
相關(guān)PDF資料
PDF描述
CY7C43626 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出)
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出)
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出)
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出)
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出)
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