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參數(shù)資料
| 型號： | CY7C43666AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出) |
| 中文描述： | 3.3 4K的x36/x18x2三總線的FIFO（3.3 4K的x36/x18x2三路總線先進(jìn)先出） |
| 文件頁數(shù)： | 3/39頁 |
| 文件大?。?/td> | 573K |
| 代理商： | CY7C43666AV |
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CY7C43646AV
CY7C43666AV/CY7C43686AV
3
PRELIMINARY
Functional Description
The CY7C436X6AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent
256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board
each chip buffer data in opposite directions. FIFO data on Port
B can be input and output in 36-bit, 18-bit, or 9-bit formats with
a choice of Big or Little Endian configurations.
The CY7C436X6AV is a synchronous (clocked) FIFO, mean-
ing each port employs a synchronous interface. All data trans-
fers through a port are gated to the LOW-to-HIGH transition of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or co-
incident. The enables for each port are arranged to provide a
simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers
’
width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X6AV: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big or Little Endian byte arrangement and
selects serial flag programming, parallel flag programming, or
one of the three possible default flag offset settings, 8, 16, or
64. Each FIFO has its own independent Master Reset pin,
MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own indepen-
dent Partial Reset pin, PRS1 and PRS2.
The CY7C436X6AV have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is de-
posited into the memory array. A read operation is required to
access that word (along with all other words residing in mem-
ory). In the First-Word Fall-Through Mode
(FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears au-
tomatically on the outputs, no read operation required (never-
theless, accessing subsequent words does necessitate a for-
mal read request). The state of the FWFT/STAN pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFC/IRC). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First Word Fall Through Mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFC).
AEA and AEB indicate when a selected number of words writ-
ten to FIFO memory achieve a predetermined
“
almost empty
state.
”
AFA and AFC indicate when a selected number of
words written to the memory achieve a predetermined
“
almost
full state.
”
IRA, IRC, AFA, and AFC are synchronized to the port clock
that writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFC are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFC threshold can be set at 8, 16, or
64 locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. Such a width expansion requires no additional ex-
ternal components.
If at any time the FIFO is not actively performing a function,
the chip will automatically power down. During the Power
Down state, supply current consumption (I
CC
) is at a minimum.
Initiating any operation (by activating control inputs) will imme-
diately take the device out of the Power Down state.
The CY7C436X6AV are characterized for operation from 0
°
C
to 70
°
C. Input ESD protection is greater than 2001V, and latch-
up is prevented by the use of guard rings.
Selection Guide
7C43646/66/86AV-7
133
6
7.5
3
0
6
60
7C43646/66/86AV-10
100
8
10
4
0
8
60
7C43646/66/86AV-15
66.7
10
15
5
0
10
60
60
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Commercial
Industrial
7C43646AV
1K x 36/x18x2
128 TQFP
7C43666AV
4K x 36/18x2
128 TQFP
7C43686AV
16K x 36/x18x2
128 TQFP
Density
Package
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686AV | 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C453 | 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級聯(lián)定時的先進(jìn)先出) |
| CY7C451 | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時的先進(jìn)先出) |
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級聯(lián)定時的先進(jìn)先出) |
| CY7C466A | Asynchronous, Cascadable 64K x9 FIFOs(異步，可級聯(lián)的 64K x9 先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
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