參數(shù)資料
型號(hào): CY7C43682
廠(chǎng)商: Cypress Semiconductor Corp.
英文描述: 16K x36 x2 Bidirectional Synchronous FIFO(16K x36 x2 雙向同步先進(jìn)先出)
中文描述: 16K的x36 x2雙向同步FIFO(16K的x36 x2雙向同步先進(jìn)先出)
文件頁(yè)數(shù): 10/31頁(yè)
文件大?。?/td> 463K
代理商: CY7C43682
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
10
PRELIMINARY
Notes:
12. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
13. t
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than t
SKEW1
, then FFB/IRB may transition HIGH one cycle later than shown.
14. Written to FIFO1.
Switching Waveforms
(continued)
Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
t
WFF
t
DS
t
ENS
t
ENH
t
DH
t
SKEW1[13]
AFA Offset (Y1)
AFB Offset (Y2)
First Word to FIFO1
CLKA
RST1, RST2
FS1, FS0
FFA/IRA
ENA
A
0
35
CLKB
FFB/IRB
[12]
AEB Offset (X1)
AEA Offset (X2)
t
FSS
t
FSH
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
DS
t
DH
t
ENS
t
ENH
t
ENS
t
ENH
HIGH
W1
[14]
W2
[14]
t
CLK
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t
ENS
t
ENH
t
ENS
t
ENH
相關(guān)PDF資料
PDF描述
CY7C43633 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進(jìn)先出帶總線(xiàn)匹配)
CY7C43623 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進(jìn)先出帶總線(xiàn)匹配)
CY7C43643 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進(jìn)先出帶總線(xiàn)匹配)
CY7C43663 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進(jìn)先出帶總線(xiàn)匹配)
CY7C43683 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進(jìn)先出帶總線(xiàn)匹配)
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