參數(shù)資料
型號: CY7C43682
廠商: Cypress Semiconductor Corp.
英文描述: 16K x36 x2 Bidirectional Synchronous FIFO(16K x36 x2 雙向同步先進先出)
中文描述: 16K的x36 x2雙向同步FIFO(16K的x36 x2雙向同步先進先出)
文件頁數(shù): 13/31頁
文件大?。?/td> 463K
代理商: CY7C43682
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
13
PRELIMINARY
Note:
18. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
CLK
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO1 Empty
LOW
HIGH
LOW
Old Data in FIFO1 Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW1[18]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A
0
35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B
0
35
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
相關(guān)PDF資料
PDF描述
CY7C43633 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進先出帶總線匹配)
CY7C43623 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進先出帶總線匹配)
CY7C43643 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進先出帶總線匹配)
CY7C43663 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進先出帶總線匹配)
CY7C43683 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進先出帶總線匹配)
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