參數(shù)資料
型號(hào): CY7C43682AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
中文描述: 3.3 16K的x36 x2雙向同步FIFO(3.3 16K的x36 x2雙向同步先進(jìn)先出)
文件頁(yè)數(shù): 18/30頁(yè)
文件大?。?/td> 458K
代理商: CY7C43682AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
18
PRELIMINARY
Note:
24. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
HIGH
HIGH
FIFO1 Full
LOW
HIGH
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[24]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO1 Output Register
Next Word From FIFO1
CLKB
CSB
W/RB
MBB
ENB
EFB/ORB
B
0
35
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)
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