參數(shù)資料
型號(hào)： CY7C43682AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
中文描述： 3.3 16K的x36 x2雙向同步FIFO（3.3 16K的x36 x2雙向同步先進(jìn)先出）
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 458K
代理商： CY7C43682AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
7
PRELIMINARY
AC Test Loads and Waveforms (-10 & -15)
AC Test Loads and Waveforms (-7)
Switching Characteristics
Over the Operating Range
Parameter
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Description
CY7C43642/
62/82AV
–
7
CY7C43642/
62/82AV
–
10
CY7C43642/
62/82AV
–
15
Unit
MHz
Min.
Max.
133
Min.
Max.
100
Min.
Max.
67
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
Pulse Duration, CLKA or CLKB LOW
Set-Up Time, A
0
–
35
before CLKA
↑
and B
0
–
35
before
CLKB
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA
↑
;
CSB, W/RB, ENB, and MBB before CLKB
↑
Set-Up Time, RST1 or RST2 LOW before CLKA
↑
or
CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before RST1 and RST2 HIGH
3.5
4
6
ns
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
t
BES
t
SDS
t
SENS
t
FWS
t
DH
t
ENH
5
7
7.5
ns
Set-Up Time, FWFT/STAN before RST1 and RST2 HIGH
Set-Up Time, FS0 before CLKA
↑
Set-Up Time, FS1 before CLKA
↑
Set-Up Time, FWFT before CLKA
↑
Hold Time, A
0
–
35
after CLKA
↑
and B
0
–
35
after CLKB
↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA
↑
;
CSB, W/RB, ENB, and MBB after CLKB
↑
Hold Time, RST1 or RST2 LOW after CLKA
↑
or CLKB
↑
[7]
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
5
7
7.5
ns
5
7
5
ns
3
4
5
ns
3
4
0
ns
0
0
0
ns
0
0
0
ns
t
RSTH
t
FSH
t
BEH
t
SDH
Note:
7.
1
2
4
ns
1
1
2
ns
Hold Time, FWFT/STAN after RST1 and RST2 HIGH
Hold Time, FS0 after CLKA
↑
1
1
2
ns
0
0
0
ns
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
3.3V
OUTPUT
R2=680
C
L
=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
R1=330
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
I/O
50
V
CC
/2
Z0=50
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