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參數(shù)資料
| 型號： | CY7C43684AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進先出帶總線匹配) |
| 中文描述： | 3.3 16K的x36 x2雙向同步FIFO瓦特/總線匹配（3.3 16K的x36 x2雙向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 25/38頁 |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43684AV |
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CY7C43644AV
CY7C43664AV/CY7C43684AV
25
PRELIMINARY
Notes:
43. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
44. D = Maximum FIFO Depth = 1K for the CY7C43644AV, 4K for the CY7C43664AV, and 16K for the CY7C43684AV.
45. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
, then AFA may transition HIGH one CLKB cycle later than shown.
46. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long-word, respectively.
47. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than t
SKEW2
, then AFB may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
t
PAF
t
ENH
t
ENS
t
PAF
t
ENS
t
ENH
[D
–
(Y1+1)] Words in FIFO1
(D
–
Y1)Words in FIFO1
t
SKEW2[45]
CLKA
ENA
AFA
CLKB
ENB
[41, 43, 44]
t
PAF
t
ENH
t
ENS
t
PAF
t
ENS
t
ENH
[D
–
(Y2+1)] Words in FIFO2
(D
–
Y2)Words in FIFO2
t
SKEW2[47]
CLKB
ENB
AFB
CLKA
ENA
Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)
[40, 44, 46]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43666AV | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進先出) |
| CY7C43686AV | 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進先出) |
| CY7C453 | 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的2Kx9可級聯(lián)定時的先進先出) |
| CY7C451 | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的512x9可級聯(lián)定時的先進先出) |
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的4Kx9可級聯(lián)定時的先進先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
| CY7C43686-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
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