參數(shù)資料
型號(hào)： CY7C43686
廠商： Cypress Semiconductor Corp.
英文描述： 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出)
中文描述： 16K的x36/x18x2三總線的FIFO（16K的x36/x18x2三路總線先進(jìn)先出）
文件頁(yè)數(shù)： 26/40頁(yè)
文件大?。?/td> 577K
代理商： CY7C43686
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
26
PRELIMINARY
Notes:
40. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
41. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
42. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
, then AEB may transition HIGH one CLKB cycle later than shown.
43. FIFO2 Write (MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
44. If Port C size is word or byte, t
is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
45. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than t
SKEW2
, then AEA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[42]
t
ENS
t
ENH
X1 Word in FIFO1
(X1+1)Words in FIFO1
CLKA
ENA
CLKB
AEB
RENB
Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[40, 41]
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[45]
t
ENS
t
ENH
X2 Word in FIFO2
(X2+1) Words in FIFO2
CLKC
WENC
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[43, 44]
相關(guān)PDF資料
PDF描述
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出)
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
CY7C43663AV 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43683AV 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43664AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43686-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
CY7C439-40DMB 制造商:Cypress Semiconductor 功能描述:
CY7C441-14JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC
CY7C441-30JC 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC
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