參數(shù)資料
型號: CY7C43686AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進先出)
中文描述: 3.3 16K的x36/x18x2三總線的FIFO(3.3 16K的x36/x18x2三路總線先進先出)
文件頁數(shù): 21/39頁
文件大小: 573K
代理商: CY7C43686AV
CY7C43646AV
CY7C43666AV/CY7C43686AV
21
PRELIMINARY
Notes:
35. If Port B size is word or byte, t
is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
36. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
HIGH
FIFO1 Full
LOW
HIGH
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[36]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO1 Output Register
Next Word From FIFO1
To FIFO1
CLKB
CSB
MBB
RENB
EFB/ORB
B
0
17
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
[35]
相關PDF資料
PDF描述
CY7C453 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的2Kx9可級聯(lián)定時的先進先出)
CY7C451 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的512x9可級聯(lián)定時的先進先出)
CY7C454 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的4Kx9可級聯(lián)定時的先進先出)
CY7C466A Asynchronous, Cascadable 64K x9 FIFOs(異步,可級聯(lián)的 64K x9 先進先出)
CY7C460A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
相關代理商/技術參數(shù)
參數(shù)描述
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
CY7C439-40DMB 制造商:Cypress Semiconductor 功能描述:
CY7C441-14JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC
CY7C441-30JC 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC
CY7C441-30JI 制造商:Rochester Electronics LLC 功能描述:- Bulk