參數(shù)資料
型號(hào)： CY7C454
廠商： Cypress Semiconductor Corp.
英文描述： 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出)
中文描述： 4Kx9級(jí)聯(lián)與時(shí)鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的4Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出）
文件頁(yè)數(shù)： 18/23頁(yè)
文件大?。?/td> 437K
代理商： CY7C454
CY7C451
CY7C453
CY7C454
18
PRELIMINARY
Boundary Flags (Full)
The Full flag is synchronized to the CKW signal (i.e., the Full
flag can only be updated by a clock pulse on the CKW pin). A
full FIFO that is read will be described with a Full flag until a
rising edge is presented to the CKW pin. When making the
transition from Full to Almost Full (or Full to Greater Than Half
Full), a clock cycle on the CKW is necessary to update the
flags to the current state. In such a state (flags showing Full
even through data has been read from the FIFO), two write
cycles are required to write data into the FIFO. The first write
serves only to update the flags to the Almost Full or Greater
Than Half Full state, while the second write inputs the data.
This first write cycle is known as the latent or flag update cycle
because it does not affect the data in the FIFO or the count
(number of words in the FIFO). It simply deasserts the Full flag.
The flag is updated regardless of the ENW state. Therefore,
the update occurs even when ENW is deasserted (HIGH),
so that a valid write is not necessary to update the flags to
correctly describe the FIFO. In this example, the read must
occur at least t
SKEW2
before the flag update cycle in order
for the FIFO to guarantee that the read will be included in
the count when CKW updates the flags. When a free-run-
ning clock is connected to CKW, the flag updates each cy-
cle. Full flag operation is similar to the Empty flag operation
described in Table 2
Non-Boundary Flags (Almost Empty, Half Full, Almost Full)
The CY7C451/453/454 feature programmable Almost Empty
and Almost Full flags. Each flag can be programmed a specific
distance from the corresponding boundary flags (Empty or
Full). The flags can be programmed to be activated at the
Empty or Full boundary, or at a distance of up to 1008
words/locations for the CY7C453 and CY7C454 (240
words/locations for the CY7C451) from the Empty/Full bound-
ary. The programming resolution is 16 words/locations. When
the FIFO contains the number of words or fewer for which the
flags have been programmed, the PAFE flag will be asserted
signifying that the FIFO is Almost Empty. When the FIFO is
within that same number of empty locations from being Full,
the PAFE will also be asserted signifying that the FIFO is
Almost Full. The HF flag is decoded to distinguish the
states.
The default distance (CY7C451/453/454 not programmed)
from where PAFE becomes active to the boundary (Empty,
Full) is 16 words/locations. The Almost Full and Almost
Empty flags can be programmed so that they are only ac-
tive at Full and Empty boundaries. However, the operation
will remain consistent with the non-boundary flag operation
that is discussed below.
Almost Empty is only updated by CKR while Half Full and Al-
most Full are updated by CKW. Non-boundary flags employ
flag update cycles similar to the boundary flag latent cycles in
order to update the FIFO status. For example, if the FIFO just
reaches the Greater than Half Full state, and then two words
are read from the FIFO, a write clock (CKW) will be required
to update the flags to the Less than Half Full state. However,
unlike the boundary flag latent cycle, the state of the enable
pin (ENW in this case) affects the operation. Therefore,
set-up and hold times for the enable pins must be met (t
SEN
and t
HEN
). If the enable pin is active during the flag update
cycle, the count and data are updated in addition to PAFE
and HF. If the enable pin is not asserted during the flag
update cycle, only the flags are updated. Table 3 and Table
4 show an example of a sequence of operations that update
the Almost Empty and Almost Full flags.
Programmable Parity
The CY7C451/453/454 also features even or odd parity
checking and generation. D
6
8
are used during a program
write to describe the parity option desired. Table 6 gives a
summary of programmable parity options. If the user elects
not to program the device, then parity is disabled. Parity
information is provided on one multi-mode output pin
(Q8/PG/PE). The three possible modes are described in
the following paragraphs. Regardless of the mode select-
ed, the OE pin retains three-state control of all 9 Q
0
8
bits.
Table 2. Empty Flag (Boundary Flag) Operation Example
Status Before Operation
Current
State of
FIFO
E/F
AFE
HF
Empty
0
0
1
Operation
Write
(ENW = 0)
Write
(ENW = 0)
Read
(ENR = X)
Read
(ENR = 0)
Read
(ENR = 0)
Write
(ENR = 0)
Read
(ENR = X)
Read
(ENR = 0)
Status After Operation
Comments
Number
of Words
in FIFO
0
Next
State
of FIFO
Empty
E/F
0
AFE
0
HF
1
Number
of words
in FIFO
1
Write
Empty
0
0
1
1
Empty
0
0
1
2
Write
Empty
0
0
1
2
AE
1
0
1
2
Flag Update
AE
1
0
1
2
AE
1
0
1
1
Read
AE
1
0
1
1
Empty
0
0
1
0
Read (transition from
Almost Empty to Empty)
Write
Empty
0
0
1
0
Empty
0
0
1
1
Empty
1
0
1
1
AE
1
0
1
1
Flag Update
AE
1
0
1
1
Empty
0
0
1
0
Read (transition from
Almost Empty to Empty)
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