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參數(shù)資料
| 型號： | CY7C4804V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V 4K x 80 Unidirectional Synchronous FIFO w/Bus Matching(2.5V 4K x 80 單向同步先進先出帶總線匹配) |
| 中文描述： | 2.5V的4K的× 80單向同步FIFO瓦特/總線匹配電壓（2.5V 4K的× 80單向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 114K |
| 代理商： | CY7C4804V25 |
ADVANCE INFORMATION
2.5V 4K/16K/64K x 80 Unidirectional
Synchronous FIFO w/Bus Matching
CY7C4808V25
CY7C4806V25
CY7C4804V25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 16, 1999
5/0251
Features
High-speed, low-power, unidirectional, first-in first-out
(FIFO) memories w/bus matching capabilities
64K x 80 (CY7C4808V25)
16K x 80 (CY7C4806V25)
4K x 80 (CY7C4804V25)
2.5V ± 125 mV power supply
Fabricated using Cypress 0.21-micron CMOS Technol-
ogy for optimum speed/power
Individual clock frequency up to 200 MHz (5 ns
read/write cycle times)
High-speed access with t
A
= 3.5
Bus matching on both ports: x80, x40, x20, x10
Free-running CLKA and CLKB. Clocks may be asyn-
chronous or coincident
CY standard or First-Word Fall-Through modes
Serial and parallel programming of Almost Empty/Full
flags, each with 3 default values (8, 16, 64)
Master and Partial reset capability
Retransmit capability
All I/Os are 1.5V HSTL
Big or Little Endian format on Port B
288 FBGA 19 mm x 19 mm (1.0-mm ball pitch) packaging
Width and depth expansion capability
Preliminary Top Level Block Diagram
Port A
Control
Logic
Port B
Control
Logic
MailBox
Register
B
B
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable Flag
Offset Registers
4K/16K/64K
x80
Dual Ported
Memory
FIFO
Reset
Logic
CLKA
CSA
ENA
MBA
MRS
PRS
FF/IR
AF
FS0/SD
FS1/SEN
A
79–0
B
79–0
CLKB
CSB
ENB
MBB
BE/FWFT
SIZE1B
SIZE2B
RT/SPM
EF/OR
AE
MBF
R
80
80
4K/16K/64K
x80
Dual Ported
Memory
SIZE1A
SIZE2A
W
IM
TDI
TCK
TMS
TRST
OE
JTAG/BIST Controller
TDO
For the most recent information, visit the Cypress web site at www.cypress.com
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C4806V25 | 2.5V 16K x 80 Unidirectional Synchronous FIFO w/Bus Matching(2.5V 16K x 80 單向同步先進先出帶總線匹配) |
| CY7C4808V25 | 2.5V 64K x 80 Unidirectional Synchronous FIFO w/Bus Matching(2.5V 64K x 80 單向同步先進先出帶總線匹配) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4821-25AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4831-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 2K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2K X9 X2 DOUBLE SYNC FIFO - Bulk |
| CY7C4831-25AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4841-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:4K X9 X2 DOUBLE SYNC FIFO - Bulk |
| CY7C4851-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 8K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:8K X9 X2 DOUBLE SYNC FIFO - Bulk |
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