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參數(shù)資料
| 型號(hào)： | CY7C4806V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V 16K x 80 Unidirectional Synchronous FIFO w/Bus Matching(2.5V 16K x 80 單向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 2.5V的16K的× 80單向同步FIFO瓦特/總線匹配電壓（2.5V 16K的× 80單向同步先進(jìn)先出帶總線匹配） |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 114K |
| 代理商： | CY7C4806V25 |
CY7C4808V25
CY7C4806V25
CY7C4804V25
ADVANCE INFORMATION
2
Functional Description
The CY7C480XV25 family of FIFOs is high-speed, low-power,
CMOS Synchronous (clocked) FIFO memories, meaning each
port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of the
clock on either port by the enable signal. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enable for each port is arranged to provide
a simple unidirectional interface between microprocessors
and/or buses with synchronous control.
Two kinds of reset are available on the CY7C480XV25: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big Endian or Little Endian byte arrange-
ment, selects the CY standard or First-Word Fall-Through
(FWFT) mode, and determines the configuration of the pro-
grammable flags. The flags can be programmed either in serial
mode or in parallel mode. The FIFO also comes with three
possible default flag offset settings: 8, 16, or 64.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings.
The CY7C480XV25 have two modes of operation: CY Stan-
dard Mode or First-Word Fall-Through Mode (FWFT). In the
CY Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the FWFT Mode, the first long-word (80-bit-wide)
written to an empty FIFO appears automatically on the out-
puts, and no read operation is required. Nevertheless, access-
ing subsequent words does necessitate a formal read request.
FWFT mode is primarily used for cascading 2 or more FIFOs.
The FIFO has an EF_OR flag on port B and FF_IR flag on Port
A. The EF and FF functions are selected in the CY Standard
Mode. EF indicates whether or not the FIFO memory is empty.
FF shows whether or not the memory is full. The IR and OR
functions are selected in the First-Word Fall-Through mode. IR
indicates whether or not the FIFO has memory locations avail-
able. OR shows whether the FIFO has data available for read-
ing or not. It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates the number
of words left in the FIFO memory is at the user-defined
amount. AF indicates the number of words written into the
FIFO memory has achieved a predetermined amount.
FF_IR and AF flags are synchronized to port A clock that
writes data into its array. EF_OR and AE flags are synchro-
nized to Port B clock that reads data from its array. Program-
mable offsets for AE and AF are loaded in parallel via Port A
or in serial via the SD input. The Serial Programming Mode pin
(SPM) makes this selection. Three default offsets setting are
also provided. The AE threshold can be set at 8, 16 or 64
locations from the empty boundary and AF threshold can be
set at 8, 16, or 64 locations from the full boundary. All these
choices are made using the FS0 and FS1 inputs during Master
Reset.
Two or more devices may be used in parallel to create wider
data paths. If, at any time, the FIFO is not actively performing
a function, the chip will automatically power down. During the
Power-Down state, supply current consumption (I
CC
) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the Power-Down state.
The CY7C480XV25 FIFOs are characterized for operation
from 0
°
C to 70
°
C commercial, and from
–
40
°
C to 85
°
C indus-
trial.
Selection Guide
CY7C480XV25-200
CY7C480XV25-166
Maximum Frequency (MHz)
200
166
Maximum Access Time (ns)
3.5
4
Minimum Cycle Time (ns)
5
6
Minimum Data or Enable Set-Up (ns)
0.6
0.6
Minimum Data or Enable Hold (ns)
0.6
0.6
Maximum Flag Delay (ns)
3.5
4
CY7C4808V25
CY7C4806V25
CY7C4804V25
Density
64K x 80
16K x 80
4K x 80
Package
288 FBGA
288 FBGA
288 FBGA
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| CY7C4808V25 | 2.5V 64K x 80 Unidirectional Synchronous FIFO w/Bus Matching(2.5V 64K x 80 單向同步先進(jìn)先出帶總線匹配) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4821-25AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4831-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 2K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2K X9 X2 DOUBLE SYNC FIFO - Bulk |
| CY7C4831-25AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4841-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:4K X9 X2 DOUBLE SYNC FIFO - Bulk |
| CY7C4851-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 8K x 9 x 2 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:8K X9 X2 DOUBLE SYNC FIFO - Bulk |
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