參數(shù)資料
型號(hào)： CY7C63310
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁(yè)數(shù)： 32/74頁(yè)
文件大?。?/td> 1441K
代理商： CY7C63310
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 32 of 74
14.2.2
When set, the corresponding interrupt is active on the falling
edge.
When clear, the corresponding interrupt is active on the rising
edge.
Int Act Low
14.2.3
When set, the input has TTL threshold. When clear, the input
has standard CMOS threshold.
TTL Thresh
14.2.4
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CY7C638xx, only the P1.7–P1.3 have 50 mA sink drive
capability. Other pins have 8 mA sink drive capability.
High Sink
14.2.5
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is
set, the pin is in high-impedance state. If the corresponding bit
in the Port Data Register is clear, the pin is driven low.
When clear, the output is driven LOW or HIGH.
Open Drain
14.2.6
When set the pin has a 7K pull up to V
CC
(or VREG for ports
with V3.3 enabled).
Pull up Enable
When clear, the pull up is disabled.
14.2.7
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
Output Enable
14.2.8
The P1.2(VREG), P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI)
and P1.6(SMISO) pins can be used for their dedicated
functions or for GPIO.
To enable the pin for GPIO, clear the corresponding VREG
Output or SPI Use bit. The SPI function controls the output
enable for its dedicated function pins when their GPIO enable
bit is clear. The VREG output is not available on the
CY7C63801 and CY7C63310.
VREG Output/SPI Use
14.2.9
The
P1.6(SMISO) pins have an alternate voltage source from the
voltage regulator. If the 3.3V Drive bit is set a high level is
driven from the voltage regulator instead of from V
CC
.
Setting the 3.3V Drive bit does not enable the voltage
regulator. That must be done explicitly by setting the VREG
Enable bit in the VREGCR Register (
Table 19-1
).
3.3V Drive
P1.3(SSEL),
P1.4(SCLK),
P1.5(SMOSI)
and
Figure 14-1. Block Diagram of a GPIO
V
CC
VREG
V
CC
VREG
GPO
PN
R
UP
Data Out
V
CC
GND
VREG
GND
3.3VDrive
Pul-Up Enabe
Output Enabe
Open Dran
Port Data
Hgh Snk
Data In
TTL Threshod
相關(guān)PDF資料
PDF描述
CY7C63801 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63823 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63813 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C63833 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
CY7C65640-LFXC TetraHub High-speed USB Hub Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C63310-PXC 功能描述:USB 接口集成電路 USB 3K Flash 128 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63310-SXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 3K/128 16-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63310-SXCES 制造商:Cypress Semiconductor 功能描述:
CY7C634121C-PVXC 制造商:Cypress Semiconductor 功能描述:
CY7C634121C-PXC 制造商:Cypress Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*