參數(shù)資料
型號(hào)： CY7C63310
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁(yè)數(shù)： 51/74頁(yè)
文件大?。?/td> 1441K
代理商： CY7C63310
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 51 of 74
18.1
USB Transceiver Configuration
Table 18-1. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
USB Pull-up
Enable
Reserved
USB Force State
Read/Write
R/W
–
–
–
–
–
–
R/W
Default
0
0
0
0
0
0
0
0
Bit 7:
USB Pull-up Enable
0 = Disable the pull-up resistor on D–
1 = Enable the pull-up resistor on D–. This pull up is to V
CC
IF VREG is not enabled or to the internally generated 3.3V when
VREG is enabled
Bit [6:1]:
Reserved
Bit 0:
USB Force State
This bit allows the state of the USB I/O pins D- and D+ to be forced to a state while USB is enabled
0 = Disable USB Force State
1 = Enable USB Force State. Allows the D- and D+ pins to be controlled by P1.1 and P1.0 respectively when the USBIO is in
USB mode. Refer to
Table 14-2
for more information
Note:
The USB transceiver has a dedicated 3.3V regulator for USB signalling purposes and to provide for the 1.5K D-pull-up.
Unlike the other 3.3V regulator, this regulator cannot be controlled/accessed by firmware. When the device is suspended, this
regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D-line is pulled up
to 5V through an alternate 6.5K resistor. During wake up following a suspend, the band gap and the regulator are switched on
in any order. Under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator
and the band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the D- line. The host can
misinterpret this as a deattach condition. This condition, although rare, can be avoided by keeping the bandgap circuitry
enabled during sleep. This is achieved by setting the ‘No Buzz’ bit, bit[5] in the OSC_CR0 register. This is an issue only if the
device is put to sleep during a bus reset condition.
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參數(shù)描述
CY7C63310-PXC 功能描述:USB 接口集成電路 USB 3K Flash 128 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63310-SXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 3K/128 16-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63310-SXCES 制造商:Cypress Semiconductor 功能描述:
CY7C634121C-PVXC 制造商:Cypress Semiconductor 功能描述:
CY7C634121C-PXC 制造商:Cypress Semiconductor 功能描述:
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