參數(shù)資料
型號(hào): CY7C63722-XC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, UUC25
封裝: DIE-25
文件頁(yè)數(shù): 13/58頁(yè)
文件大?。?/td> 1236K
代理商: CY7C63722-XC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 13 of 58
8.3
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into
the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X
to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that
specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.
Note:
All bits of all registers are cleared to all zeros on reset,
except the Processor Status and Control Register (
Figure 20-1
).
All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written
as 0 and be treated as undefined by reads.
I/O Register Summary
Table 8-1. I/O Register Summary
Register Name
Port 0 Data
Port 1 Data
Port 2 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Port 0 Mode0
Port 0 Mode1
Port 1 Mode0
Port 1 Mode1
I/O Address
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x0A
0x0B
0x0C
0x0D
Read/Write
R/W
R/W
R
W
W
W
W
W
W
W
W
Function
Fig.
12-2
12-3
12-8
21-4
21-5
21-6
21-7
12-4
12-5
12-6
12-7
GPIO Port 0
GPIO Port 1
Auxiliary input register for D+, D–, VREG, XTALIN
Interrupt enable for pins in Port 0
Interrupt enable for pins in Port 1
Interrupt polarity for pins in Port 0
Interrupt polarity for pins in Port 1
Controls output configuration for Port 0
Controls output configuration for Port 1
USB Device Address
EP0 Counter Register
EP0 Mode Register
EP1 Counter Register
EP1 Mode Register
EP2 Counter Register
EP2 Mode Register
USB Status & Control
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x1F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USB Device Address register
USB Endpoint 0 counter register
USB Endpoint 0 configuration register
USB Endpoint 1 counter register
USB Endpoint 1 configuration register
USB Endpoint 2 counter register
USB Endpoint 2 configuration register
USB status and control register
14-1
14-4
14-2
14-4
14-3
14-4
14-3
13-1
Global Interrupt Enable
Endpoint Interrupt Enable
Timer (LSB)
Timer (MSB)
WDR Clear
0x20
0x21
0x24
0x25
0x26
R/W
R/W
R
R
W
Global interrupt enable register
USB endpoint interrupt enables
Lower 8 bits of free-running timer (1 MHz)
Upper 4 bits of free-running timer
Watchdog Reset clear
21-1
21-2
18-1
18-2
-
Capture Timer A Rising
Capture Timer A Falling
Capture Timer B Rising
Capture Timer B Falling
Capture TImer Configuration
Capture Timer Status
0x40
0x41
0x42
0x43
0x44
0x45
R
R
R
R
Rising edge Capture Timer A data register
Falling edge Capture Timer A data register
Rising edge Capture Timer B data register
Falling edge Capture Timer B data register
Capture Timer configuration register
Capture Timer status register
19-2
19-3
19-4
19-5
19-7
19-6
R/W
R
SPI Data
SPI Control
0x60
0x61
R/W
R/W
SPI read and write data register
SPI status and control register
17-2
17-3
Clock Configuration
Processor Status & Control
0xF8
0xFF
R/W
R/W
Internal / External Clock configuration register
Processor status and control
9-2
20-1
相關(guān)PDF資料
PDF描述
CY7C63723-SC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743-SC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63722 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
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