參數(shù)資料
型號(hào)： CY7C63722-XC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, UUC25
封裝： DIE-25
文件頁(yè)數(shù)： 34/58頁(yè)
文件大?。?/td> 1236K
代理商： CY7C63722-XC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 34 of 58
Bit [7:4]:
Reserved.
Bit [3:0]: Capture A/B, Falling/Rising Event
These bits record the occurrence of any rising or falling edges on the capture GPIO pins. Bits in this register are cleared by
reading the corresponding data register.
1 = A rising or falling event that matches the pin’s rising/falling condition has occurred.
0 = No event that matches the pin’s rising or falling edge condition.
Because both Capture A events (rising and falling) share an interrupt, user’s firmware needs to check the status of both
Capture A Falling and Rising Event bits to determine what caused the interrupt. This is also true for Capture B events.
Bit 7: First Edge Hold
1 = The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read. Subsequent
edges are ignored until the Capture Timer Data Register is read.
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture A Falling Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture B Rising Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture B Falling Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
Capture B
Falling
Event
Capture B
Rising
Event
Capture A
Falling
Event
Capture A
Rising
Event
Read/Write
-
-
-
-
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-6. Capture Timer Status Register (Address 0x45)
Bit #
7
6
5
4
3
2
1
0
Bit Name
First Edge
Hold
Prescale Bit [2:0]
Capture B
Falling
Int Enable
Capture B
Rising
Int Enable
Capture A
Falling
Int Enable
Capture A
Rising
Int Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 19-7. Capture Timer Configuration Register (Address 0x44)
相關(guān)PDF資料
PDF描述
CY7C63723-SC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743-SC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63722 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
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