參數(shù)資料
型號(hào): CY7C63723-PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDIP18
封裝: 0.300 INCH, PLASTIC, DIP-18
文件頁數(shù): 19/58頁
文件大?。?/td> 1236K
代理商: CY7C63723-PC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 19 of 58
Port 0 is an 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0 in the CY7C63723, or all 8 bits, P1.7–P1.0 in the CY7C63743 parts.
Each bit can also be selected as an interrupt source for the microcontroller, as explained in Section 21.0.
The data for each GPIO pin is accessible through the Port Data register. Writes to the Port Data register store outgoing data state
for the port pins, while reads from the Port Data register return the actual logic value on the port pins, not the Port Data register
contents.
Each GPIO pin is configured independently. The driving state of each GPIO pin is determined by the value written to the pin’s
Data Register and by two associated pin’s Mode0 and Mode1 bits.
The Port 0 Data Register is shown in
Figure 12-2
, and the Port 1 Data Register is shown in
Figure 12-3
. The Mode0 and Mode1
bits for the two GPIO ports are given in
Figure 12-4
through
Figure 12-7
.
Bit [7:0]: P0[7:0]
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 12-2. Port 0 Data (Address 0x00)
Bit #
7
6
5
4
3
2
1
0
Bit Name
P1
Notes
Pins 7:2 only in CY7C63743
Pins 1:0 in all parts
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 12-3. Port 1 Data (Address 0x01)
GPIO
Pin
V
CC
14 k
GPIO
Mode
Data
Out
Register
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
Logic
C
To Interrupt
Controller
Q1
Q2
Q3
To Capture Timers (P0.0, P0.1)
and SPI (P0.4–P0.7))
Interrupt
Polarity
2
Threshold Select
SPI Bypass (P0.5–P0.7 only)
(=1 if SPI inactive, or for non-SPI pins)
(Data Reg must be 1
for SPI outputs)
Figure 12-1. Block Diagram of GPIO Port (one pin shown)
相關(guān)PDF資料
PDF描述
CY7C63743 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63723C enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器)
CY7C63803 enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
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CY7C63723-SCT 制造商:Cypress Semiconductor 功能描述:I/O Controller USB and PS/2 Controller 0.02A 18-Pin SOIC T/R
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