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參數(shù)資料
| 型號： | CY7C63723-PC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDIP18 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件頁數(shù)： | 35/58頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | CY7C63723-PC |
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FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 35 of 58
0 = The time of the most recent edge is held in the Capture Timer Data Register. That is, if multiple edges have occurred before
reading the capture timer, the time for the last one will be read (default state).
The First Edge Hold function applies globally to all four capture timers.
Bit [6:4]: Prescale Bit [2:0]
Three prescaler bits allow the capture timer clock rate to be selected among 5 choices, as shown in
Table 19-1
Bit [3:0]: Capture A/B, Rising/Falling Interrupt Enable
Each of the four Capture Timer registers can be individually enabled to provide interrupts.
Both Capture A events share a common interrupt request, as do the two Capture B events. In addition to the event enables,
the main Capture Interrupt Enables bit in the Global Interrupt Enable register (Section 21.0) must be set to activate a capture
interrupt.
1 = Enable interrupt
0 = Disable interrupt
20.0
Processor Status and Control Register
Bit 7: IRQ Pending
When an interrupt is generated, it is registered as a pending interrupt. The interrupt will remain pending until its interrupt enable
bit is set (
Figure 21-1
and
Figure 21-2
) and interrupts are globally enabled (Bit 2, Processor Status and Control Register). At
that point the internal interrupt handling sequence will clear the IRQ Pending bit until another interrupt is detected as pending.
This bit is only valid if the Global Interrupt Enable bit is disabled.
1 = There are pending interrupts.
0 = No pending interrupts.
Bit 6: Watchdog Reset
The Watchdog Timer Reset (WDR) occurs when the internal Watchdog timer rolls over. The timer will roll over and WDR will
occur if it is not cleared within t
WATCH
(see Section 26.0 for the value of t
WATCH
). This bit is cleared by an LVR/BOR. Note that
a watchdog reset can occur with a POR/LVR/BOR event, as discussed at the end of this section.
1 = A watchdog reset occurs.
0 = No watchdog reset
Bit 5: Bus Interrupt Event
The Bus Reset Status is set whenever the event for the USB Bus Reset or PS/2 Activity interrupt occurs. The event type (USB
or PS/2) is selected by the state of the USB-PS/2 Interrupt Mode bit in the USB Status and Control Register (see
Figure 13-1
).
The details on the event conditions that set this bit are given in Section 21.3. In either mode, this bit is set as soon as the event
Table 19-1. Capture Timer Prescalar Settings (Step size and range for F
CLK
= 6 MHz)
Prescale 2:0
Captured Bits
LSB Step Size
1
μ
s
2
μ
s
4
μ
s
8
μ
s
16
μ
s
Range
256
μ
s
512
μ
s
000
Bits 7:0 of free-running timer
001
Bits 8:1 of free-running timer
010
Bits 9:2 of free-running timer
1.024 ms
011
Bits 10:3 of free-running timer
2.048 ms
100
Bits 11:4 of free-running timer
4.096 ms
Bit #
7
6
5
4
3
2
1
0
Bit Name
IRQ
Pending
Watchdog
Reset
Bus
Interrupt
Event
LVR/BOR
Reset
Suspend
Interrupt
Enable
Sense
Reserved
Run
Read/Write
R
R/W
R/W
R/W
R/W
R
-
R/W
Reset
0
1
0
1
0
0
0
1
Figure 20-1. Processor Status and Control Register (Address 0xFF)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C63743 | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| CY7C63743-PC | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| CY7C63743C | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| CY7C63723C | enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller(enCoRe USB結(jié)合低速USB和PS/2外設(shè)控制器) |
| CY7C63803 | enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63723-PXC | 功能描述:IC MCU 8K USB/PS2 LS 18DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63723-SC | 功能描述:IC MCU 8K LS USB/PS-2 18-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63723-SCT | 制造商:Cypress Semiconductor 功能描述:I/O Controller USB and PS/2 Controller 0.02A 18-Pin SOIC T/R |
| CY7C63723-SXC | 功能描述:IC MCU 8K LS USB/PS-2 18-SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63723-SXCT | 制造商:Cypress Semiconductor 功能描述:I/O Controller USB and PS/2 Controller 0.02A 18-Pin SOIC T/R |
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