參數(shù)資料
型號(hào): CY7C63723-SC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO18
封裝: 0.300 INCH, PLASTIC, MO-119, SOIC-18
文件頁(yè)數(shù): 16/58頁(yè)
文件大小: 1236K
代理商: CY7C63723-SC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 16 of 58
9.2
The user can connect a low-cost ceramic resonator or an external oscillator to the XTALIN/XTALOUT pins to provide a precise
reference frequency for the chip clock, as shown in
Figure 9-1
. The external components required are a ceramic resonator or
crystal and any associated capacitors. To run from the external resonator, the External Oscillator Enable bit of the Clock Config-
uration Register must be set to 1, as explained in the previous section.
Start-up times for the external oscillator depend on the resonating device. Ceramic resonator based oscillators typically start in
less than 100
μ
s, while crystal based oscillators take longer, typically 1 to 10 ms. Board capacitance should be minimized on the
XTALIN and XTALOUT pins by keeping the traces as short as possible.
An external 6-MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open.
External Oscillator
10.0
Reset
The USB Controller supports three types of resets. The effects of the reset are listed below. The reset types are:
1. Low-voltage Reset (LVR)
2. Brown Out Reset (BOR)
3. Watchdog Reset (WDR)
The occurrence of a reset is recorded in the Processor Status and Control Register (
Figure 20-1
). Bits 4 (Low-voltage or Brown-out
Reset bit) and 6 (Watchdog Reset bit) are used to record the occurrence of LVR/BOR and WDR respectively. The firmware can
interrogate these bits to determine the cause of a reset.
The microcontroller begins execution from ROM address 0x0000 after a LVR, BOR, or WDR reset. Although this looks like
interrupt vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero
flag onto program stack. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution
results.
The following events take place on reset. More details on the various resets are given in the following sections.
1. All registers are reset to their default states (all bits cleared, except in Processor Status and Control Register).
2. GPIO and USB pins are set to high-impedance state.
3. The VREG pin is set to high-impedance state.
4. Interrupts are disabled.
5. USB operation is disabled and must be enabled by firmware if desired, as explained in Section 14.1.
6. For a BOR or LVR, the external oscillator is disabled and Internal Clock mode is activated, followed by a time-out period t
START
for V
CC
to stabilize. A WDR does not change the clock mode, and there is no delay for V
CC
stabilization on a WDR. Note that
the External Oscillator Enable (Bit 0,
Figure 9-2
) will be cleared by a WDR, but it does not take effect until suspend mode is
entered.
7. The Program Stack Pointer (PSP) and Data Stack Pointer (DSP) reset to address 0x00. Firmware should move the DSP for
USB applications, as explained in Section 6.5.
8. Program execution begins at address 0x0000 after the appropriate time-out period.
10.1
When V
CC
is first applied to the chip, the internal oscillator is started and the Low-voltage Reset is initially enabled by default. At
the point where V
CC
has risen above V
LVR
(see Section 25.0 for the value of V
LVR
), an internal counter starts counting for a period
of t
START
(see Section 26.0 for the value of t
START
). During this t
START
time, the microcontroller enters a partial suspend state to
wait for V
CC
to stabilize before it begins executing code from address 0x0000.
As long as the LVR circuit is enabled, this reset sequence repeats whenever the V
CC
pin voltage drops below V
LVR
. The LVR can
be disabled by firmware by setting the Low-voltage Reset Disable bit in the Clock Configuration Register (
Figure 9-2
). In addition,
the LVR is automatically disabled in suspend mode to save power. If the LVR was enabled before entering suspend mode, it
When LVR is disabled during normal operation (i.e., by writing ‘0’ to the Low-voltage Reset Disable bit in the Clock Configuration
Register), the chip may enter an unknown state if V
CC
drops below V
LVR
. Therefore, LVR should be enabled at all times during
normal operation. If LVR is disabled (i.e., by firmware or during suspend mode), a secondary low-voltage monitor, BOR, becomes
active, as described in the next section. The LVR/BOR Reset bit of the Processor Status and Control Register (
Figure 20-1
), is
set to ‘1’ if either a LVR or BOR has occurred.
Low-voltage Reset (LVR)
10.2
The Brown Out Reset (BOR) circuit is always active and behaves like the POR. BOR is asserted whenever the V
CC
voltage to
the device is below an internally defined trip voltage of approximately 2.5V. The BOR re-enables LVR. That is, once V
CC
drops
Brown Out Reset (BOR)
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CY7C63743-SC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
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