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參數(shù)資料
| 型號(hào)： | CY7C63723-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO18 |
| 封裝： | 0.300 INCH, PLASTIC, MO-119, SOIC-18 |
| 文件頁數(shù)： | 37/58頁 |
| 文件大小： | 1236K |
| 代理商： | CY7C63723-SC |
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FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 37 of 58
When servicing an interrupt, the hardware will first disable all interrupts by clearing the Global Interrupt Enable bit in the CPU (the
state of this bit can be read at Bit 2 of the Processor Status and Control Register). Next, the flip-flop of the current interrupt is
cleared. This is followed by an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e.,
the Interrupt Vector, see Section 21.1). The instruction in the interrupt table is typically a JMP instruction to the address of the
Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction.
Interrupts can be nested to a level limited only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used just before the RETI instruction to
restore the accumulator value. The program counter, CF and ZF are restored and interrupts are enabled when the RETI instruction
is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
21.1
The Interrupt Vectors supported by the device are listed in
Table 21-1
. The highest priority interrupt is #1 (USB Bus Reset / PS/2
activity), and the lowest priority interrupt is #11 (Wake-up Timer). Although Reset is not an interrupt, the first instruction executed
after a reset is at ROM address 0x0000, which corresponds to the first entry in the Interrupt Vector Table. Interrupt vectors occupy
two bytes to allow for a two-byte JMP instruction to the appropriate Interrupt Service Routine (ISR).
Interrupt Vectors
21.2
Interrupt latency can be calculated from the following equation:
Interrupt Latency =
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. With a 6-MHz external resonator, internal CPU clock speed is 12 MHz, so 20 clocks take 20/12 MHz = 1.67
μ
s.
Interrupt Latency
21.3
The following sections provide details on the different types of interrupt sources.
Interrupt Sources
Table 21-1. Interrupt Vector Assignments
Interrupt Vector Number
ROM Address
Function
not applicable
0x0000
Execution after Reset begins here
1
0x0002
USB Bus Reset or PS/2 Activity interrupt
128-
μ
s timer interrupt
2
0x0004
3
1.024-ms timer interrupt
4
0x0008
USB Endpoint 0 interrupt
5
0x000A
USB Endpoint 1 interrupt
6
0x000C
USB Endpoint 2 interrupt
7
0x000E
SPI Interrupt
8
0x0010
Capture Timer A interrupt
9
0x0012
Capture Timer B interrupt
10
0x0014
GPIO interrupt
11
0x0016
Wake-up Timer interrupt
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C63743-SC | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| CY7C63722 | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| CY7C63723 | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| CY7C63723-PC | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
| CY7C63743 | enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63723-SCT | 制造商:Cypress Semiconductor 功能描述:I/O Controller USB and PS/2 Controller 0.02A 18-Pin SOIC T/R |
| CY7C63723-SXC | 功能描述:IC MCU 8K LS USB/PS-2 18-SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63723-SXCT | 制造商:Cypress Semiconductor 功能描述:I/O Controller USB and PS/2 Controller 0.02A 18-Pin SOIC T/R |
| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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